Counter Matrix Code for SRAM Based FPGA to Correct Multi Bit Upset Error

Memory blocks are the most significant features of any design, frothy of its silicon area, functionality and dependency. SRAM memories are the main benefactors to the Soft Error Rate of the system. Since error detecting and correcting codes are commonly available and especially effective against most types of Single Event Effects, Multiple Bit Upsets and advanced errors gathering may conquer the error correction capabilities. Existing techniques use error correction codes with significantly high overhead to reduce MBUs in configuration frames, here a low-cost error-detection code to detect MBUs in configuration frames as well as a Counter Matrix Code (CMC) based on correction method is proposed. The proposed plan does not demand any alteration to the FPGA architecture. Implementation of the proposed plan on a Xilinx Virtex-6 FPGA devices displays that it can detect 100% of MBUs in the configuration frames.